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| version 1.1, 2004/08/01 05:31:32 | version 1.7, 2004/08/14 12:16:18 |
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| Line 11 | Line 11 |
| #include "parts.h" | #include "parts.h" |
| #include "z80core.h" | #include "z80core.h" |
| #include "z80c.h" | #include "z80c.h" |
| #include "x1_io.h" | #include "pccore.h" |
| #include "iocore.h" | |
| #include "z80c.mcr" | #include "z80c.mcr" |
| Line 123 void CPUCALL z80c_reset(void) { | Line 124 void CPUCALL z80c_reset(void) { |
| R_Z80R = rand_get(); | R_Z80R = rand_get(); |
| } | } |
| REG8 CPUCALL z80c_ableinterrupt(void) { | |
| return((Z80_IFF & ((1 << IFF_IFLAG) | (1 << IFF_IRQ) | (1 << IFF_NMI))) | |
| ?0:1); | |
| } | |
| void CPUCALL z80c_interrupt(REG8 vect) { | void CPUCALL z80c_interrupt(REG8 vect) { |
| REG16 pc; | REG16 pc; |
| Line 137 void CPUCALL z80c_interrupt(REG8 vect) { | Line 132 void CPUCALL z80c_interrupt(REG8 vect) { |
| Z80_IFF ^= (1 << IFF_HALT); | Z80_IFF ^= (1 << IFF_HALT); |
| R_Z80PC++; | R_Z80PC++; |
| } | } |
| Z80_IFF |= (1 << IFF_IRQ) | (1 << IFF_IFLAG); | |
| switch(R_Z80IM) { | |
| case 0: | |
| if ((vect != 0xdd) && (vect != 0xed) && (vect != 0xfd)) { | |
| Z80_COUNT(cycles_main[vect]); | |
| z80c_mainop[vect](); | |
| } | |
| break; | |
| case 1: | |
| Z80_COUNT(11); | |
| R_Z80SP -= 2; | |
| Z80_WRMEM_W(R_Z80SP, R_Z80PC); | |
| R_Z80PC = 0x38; | |
| break; | |
| case 2: | |
| pc = Z80_RDMEM_W((R_Z80I << 8) + vect); | |
| R_Z80SP -= 2; | |
| Z80_WRMEM_W(R_Z80SP, R_Z80PC); | |
| R_Z80PC = pc; | |
| break; | |
| } | |
| } | |
| void CPUCALL z80c_interrupt2(REG8 vect) { | |
| REG16 pc; | |
| if (Z80_IFF & (1 << IFF_HALT)) { | |
| Z80_IFF ^= (1 << IFF_HALT); | |
| R_Z80PC++; | |
| } | |
| Z80_IFF |= (1 << IFF_IFLAG); | Z80_IFF |= (1 << IFF_IFLAG); |
| switch(R_Z80IM) { | switch(R_Z80IM) { |
| case 0: | case 0: |
| Line 182 void CPUCALL z80c_interrupt2(REG8 vect) | Line 144 void CPUCALL z80c_interrupt2(REG8 vect) |
| case 1: | case 1: |
| Z80_COUNT(11); | Z80_COUNT(11); |
| R_Z80SP -= 2; | R_Z80SP -= 2; |
| Z80_WRMEM_W(R_Z80SP, R_Z80PC); | mem_write16(R_Z80SP, R_Z80PC); |
| R_Z80PC = 0x38; | R_Z80PC = 0x38; |
| break; | break; |
| case 2: | case 2: |
| pc = Z80_RDMEM_W((R_Z80I << 8) + vect); | pc = mem_read16((R_Z80I << 8) + vect); |
| R_Z80SP -= 2; | R_Z80SP -= 2; |
| Z80_WRMEM_W(R_Z80SP, R_Z80PC); | mem_write16(R_Z80SP, R_Z80PC); |
| R_Z80PC = pc; | R_Z80PC = pc; |
| break; | break; |
| } | } |
| Line 204 void CPUCALL z80c_nonmaskedinterrupt(voi | Line 166 void CPUCALL z80c_nonmaskedinterrupt(voi |
| R_Z80PC++; | R_Z80PC++; |
| } | } |
| R_Z80SP -= 2; | R_Z80SP -= 2; |
| Z80_WRMEM_W(R_Z80SP, R_Z80PC); | mem_write16(R_Z80SP, R_Z80PC); |
| R_Z80PC = 0x66; | R_Z80PC = 0x66; |
| } | } |
| } | } |
| Line 213 void CPUCALL z80c_execute(void) { | Line 175 void CPUCALL z80c_execute(void) { |
| UINT op; | UINT op; |
| R_Z80R++; | if (!dma.working) { |
| GET_PC_BYTE(op); | do { |
| Z80_COUNT(cycles_main[op]); | R_Z80R++; |
| z80c_mainop[op](); | GET_PC_BYTE(op); |
| Z80_COUNT(cycles_main[op]); | |
| z80c_mainop[op](); | |
| } while(CPU_REMCLOCK > 0); | |
| } | |
| else { | |
| do { | |
| R_Z80R++; | |
| GET_PC_BYTE(op); | |
| Z80_COUNT(cycles_main[op]); | |
| z80c_mainop[op](); | |
| z80dmap(); | |
| } while(CPU_REMCLOCK > 0); | |
| } | |
| } | |
| void CPUCALL z80c_step(void) { | |
| UINT op; | |
| R_Z80R++; | R_Z80R++; |
| GET_PC_BYTE(op); | GET_PC_BYTE(op); |
| Z80_COUNT(cycles_main[op]); | Z80_COUNT(cycles_main[op]); |
| z80c_mainop[op](); | z80c_mainop[op](); |
| z80dmap(); | |
| } | } |