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| version 1.2, 2004/08/08 14:00:56 | version 1.6, 2005/02/04 06:42:14 |
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| Line 6 | Line 6 |
| // | // |
| //---------------------------------------------------------------------------- | //---------------------------------------------------------------------------- |
| // #define PCCOUNTER | |
| #if defined(TRACE) && defined(PCCOUNTER) | |
| extern UINT pccnt; | |
| extern UINT pccnt2; | |
| extern UINT pccnt3; | |
| extern UINT lastpc; | |
| #endif | |
| #define Z80_COUNT(clock) \ | #define Z80_COUNT(clock) \ |
| do { \ | do { \ |
| Z80_ICOUNT += (clock); \ | CPU_REMCLOCK -= (clock); \ |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| #define Z80IRQCHECKTERM \ | |
| do { } while (/*CONSTCOND*/ 0) | |
| #if defined(TRACE) && defined(PCCOUNTER) | |
| #define GET_PC_BYTE(b) \ | |
| do { \ | |
| if ((lastpc ^ R_Z80PC) & 0x8000) { \ | |
| TRACEOUT(("%.4x->%.4x", lastpc, R_Z80PC)); \ | |
| lastpc = R_Z80PC; \ | |
| pccnt2++; \ | |
| } \ | |
| pccnt++; \ | |
| (b) = mem_read8(R_Z80PC++); \ | |
| } while (/*CONSTCOND*/ 0) | |
| #define GET_PC_WORD(w) \ | |
| do { \ | |
| pccnt3++; \ | |
| (w) = mem_read16(R_Z80PC); \ | |
| R_Z80PC += 2; \ | |
| } while (/*CONSTCOND*/ 0) | |
| #else | |
| #define GET_PC_BYTE(b) \ | #define GET_PC_BYTE(b) \ |
| do { \ | do { \ |
| (b) = mem_read8(R_Z80PC++); \ | (b) = mem_read8(R_Z80PC++); \ |
| Line 26 | Line 50 |
| (w) = mem_read16(R_Z80PC); \ | (w) = mem_read16(R_Z80PC); \ |
| R_Z80PC += 2; \ | R_Z80PC += 2; \ |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| #endif | |
| #define MCR_EX1(r1, r2) \ | #define MCR_EX1(r1, r2) \ |
| Line 66 | Line 91 |
| #define MCR_INC(reg) { \ | #define MCR_INC(reg) { \ |
| R_Z80F &= C_FLAG; \ | R_Z80F &= C_FLAG; \ |
| R_Z80F |= z80inc_flag2[(reg)]; \ | |
| (reg)++; \ | (reg)++; \ |
| R_Z80F |= z80inc_flag[(reg)]; \ | |
| } | } |
| #define MCR_DEC(reg) { \ | #define MCR_DEC(reg) { \ |
| R_Z80F &= C_FLAG; \ | R_Z80F &= C_FLAG; \ |
| R_Z80F |= z80dec_flag2[(reg)]; \ | |
| (reg)--; \ | (reg)--; \ |
| R_Z80F |= z80dec_flag[(reg)]; \ | |
| } | } |
| #define LDB_b(reg) { \ | #define LDB_b(reg) { \ |
| Line 193 | Line 218 |
| } \ | } \ |
| } \ | } \ |
| R_Z80A = (UINT8)dst; \ | R_Z80A = (UINT8)dst; \ |
| R_Z80F = flg | ZSPtable[dst & 0xff]; \ | R_Z80F = flg | z80szp_flag[dst & 0xff]; \ |
| } | } |
| #define MCR_JRFLG(flg) { \ | #define MCR_JRFLG(flg) { \ |
| Line 226 | Line 251 |
| } | } |
| #define MCR_INC_MEM(adrs) { \ | #define MCR_INC_MEM(adrs) { \ |
| UINT8 tmp; \ | REG8 tmp; \ |
| tmp = mem_read8((adrs)); \ | tmp = mem_read8((adrs)); \ |
| tmp++; \ | |
| mem_write8((adrs), tmp); \ | |
| R_Z80F &= C_FLAG; \ | R_Z80F &= C_FLAG; \ |
| R_Z80F |= z80inc_flag[tmp]; \ | R_Z80F |= z80inc_flag2[tmp]; \ |
| mem_write8((adrs), (REG8)(tmp + 1)); \ | |
| } | } |
| #define MCR_DEC_MEM(adrs) { \ | #define MCR_DEC_MEM(adrs) { \ |
| UINT8 tmp; \ | REG8 tmp; \ |
| tmp = mem_read8((adrs)); \ | tmp = mem_read8((adrs)); \ |
| tmp--; \ | |
| mem_write8((adrs), tmp); \ | |
| R_Z80F &= C_FLAG; \ | R_Z80F &= C_FLAG; \ |
| R_Z80F |= z80dec_flag[tmp]; \ | R_Z80F |= z80dec_flag2[tmp]; \ |
| mem_write8((adrs), (REG8)(tmp - 1)); \ | |
| } | } |
| #define LDB_xhl_b { \ | #define LDB_xhl_b { \ |
| Line 275 | Line 298 |
| #define MCR_HALT { \ | #define MCR_HALT { \ |
| R_Z80PC--; \ | R_Z80PC--; \ |
| Z80_IFF |= (1 << IFF_HALT); \ | Z80_IFF |= (1 << IFF_HALT); \ |
| Z80IRQCHECKTERM; \ | CPU_REMCLOCK = 0; \ |
| } | } |
| Line 343 | Line 366 |
| #define MCR_AND(b) { \ | #define MCR_AND(b) { \ |
| R_Z80A &= (b); \ | R_Z80A &= (b); \ |
| R_Z80F = ZSPtable[R_Z80A]; \ | R_Z80F = z80szp_flag[R_Z80A]; \ |
| } | } |
| #define MCR_AND_XHL { \ | #define MCR_AND_XHL { \ |
| Line 354 | Line 377 |
| #define MCR_XOR(b) { \ | #define MCR_XOR(b) { \ |
| R_Z80A ^= (b); \ | R_Z80A ^= (b); \ |
| R_Z80F = ZSPtable[R_Z80A]; \ | R_Z80F = z80szp_flag[R_Z80A]; \ |
| } | } |
| #define MCR_XOR_XHL { \ | #define MCR_XOR_XHL { \ |
| Line 366 | Line 389 |
| #define MCR_OR(b) { \ | #define MCR_OR(b) { \ |
| R_Z80A |= (b); \ | R_Z80A |= (b); \ |
| R_Z80F = ZSPtable[R_Z80A]; \ | R_Z80F = z80szp_flag[R_Z80A]; \ |
| } | } |
| #define MCR_OR_XHL { \ | #define MCR_OR_XHL { \ |
| Line 566 | Line 589 |
| } | } |
| #define MCR_EI { \ | #define MCR_EI { \ |
| UINT op; \ | REG8 iff; \ |
| Z80_IFF &= ~(1 << IFF_IFLAG); \ | SINT32 rem; \ |
| op = mem_read8(R_Z80PC); \ | iff = Z80_IFF; \ |
| if (op != 0xfb) { \ | if (iff & (1 << IFF_IFLAG)) { \ |
| R_Z80PC++; \ | Z80_IFF = (UINT8)(iff & (~(1 << IFF_IFLAG))); \ |
| R_Z80R++; \ | rem = CPU_REMCLOCK - 1; \ |
| Z80_COUNT(cycles_main[op]); \ | if ((rem < 0) || \ |
| z80c_mainop[op](); \ | ((!(iff & (1 << IFF_NMI))) && (CPU_REQIRQ != 0))) { \ |
| CPU_BASECLOCK -= rem; \ | |
| CPU_REMCLOCK = 1; \ | |
| } \ | |
| } \ | } \ |
| } | } |