|
version 1.3, 2004/08/05 11:30:13
|
version 1.7, 2004/08/11 12:08:17
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|
Line 18 void z80dmap(void) {
|
Line 18 void z80dmap(void) {
|
| r = dma.DMA_CMND; |
r = dma.DMA_CMND; |
| if ((r & 3) == 0) return; |
if ((r & 3) == 0) return; |
| if (dma.DMA_ENBL == 0) return; |
if (dma.DMA_ENBL == 0) return; |
| if (dma.ENDB_FLG != 0) return; |
if (dma.ENDB_FLG != 0) return; // mod |
| if (r & 2) { |
if (r & 2) { |
| if (dma.MACH_FLG != 0) return; |
if (dma.MACH_FLG != 0) return; // mod |
| } |
} |
| if (dma.DMA_MODE != 1) { |
if (dma.DMA_MODE != 1) { |
| if ((dma.WR[5] ^ dma.DMA_REDY) & 8) return; |
if ((dma.WR[5] ^ dma.DMA_REDY) & 8) return; |
|
Line 48 void z80dmap(void) {
|
Line 48 void z80dmap(void) {
|
| } |
} |
| addr = *off1; |
addr = *off1; |
| if (flag1 & 8) { |
if (flag1 & 8) { |
| if (addr == 0x0ffb) { |
|
| fdcdummyread = 0; |
|
| } |
|
| dat = iocore_inp(addr); |
dat = iocore_inp(addr); |
| } |
} |
| else { |
else { |
| dat = Z80_RDMEM((REG16)addr); |
dat = mem_read8(addr); |
| } |
} |
| if (dma.DMA_CMND & 1) { |
if (dma.DMA_CMND & 1) { |
| addr = *off2; |
addr = *off2; |
| if (flag2 & 8) { |
if (flag2 & 8) { |
| if ((addr == 0x0ffb) && (!ppi.IO_MODE)) { |
|
| fdcdummyread = 0; |
|
| } |
|
| iocore_out(addr, dat); |
iocore_out(addr, dat); |
| } |
} |
| else { |
else { |
| Z80_WRMEM((REG16)addr, dat); |
mem_write8(addr, dat); |
| } |
} |
| } |
} |
| if (dma.DMA_CMND & 2) { |
if (dma.DMA_CMND & 2) { |
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