| version 1.7, 2004/08/11 12:08:17 | version 1.9, 2004/08/14 12:16:18 | 
| Line 2 | Line 2 | 
 | #include        "z80core.h" | #include        "z80core.h" | 
 | #include        "pccore.h" | #include        "pccore.h" | 
 | #include        "iocore.h" | #include        "iocore.h" | 
 |  | #include        "ievent.h" | 
 |  |  | 
 |  |  | 
 | void z80dmap(void) { | void z80dmap(void) { | 
 |  |  | 
 | REG8    r; |  | 
 | UINT16  *off1; | UINT16  *off1; | 
 | UINT16  *off2; | UINT16  *off2; | 
 | REG8    flag1; | REG8    flag1; | 
 | REG8    flag2; | REG8    flag2; | 
 | UINT    addr; | UINT    addr; | 
 | REG8    dat; | REG8    dat; | 
 | REG8    vect; |  | 
 |  |  | 
| r = dma.DMA_CMND; | if (!dma.working) { | 
| if ((r & 3) == 0) return; | return; | 
| if (dma.DMA_ENBL == 0) return; |  | 
| if (dma.ENDB_FLG != 0) return;                          // mod |  | 
| if (r & 2) { |  | 
| if (dma.MACH_FLG != 0) return;                  // mod |  | 
| } |  | 
| if (dma.DMA_MODE != 1) { |  | 
| if ((dma.WR[5] ^ dma.DMA_REDY) & 8) return; |  | 
 | } | } | 
 |  |  | 
 | if (dma.WR[0] & 4) { | if (dma.WR[0] & 4) { | 
| Line 40  void z80dmap(void) { | Line 32  void z80dmap(void) { | 
 | } | } | 
 |  |  | 
 | do {            // dma_lp | do {            // dma_lp | 
| if (dma.ENDB_FLG) { | if (dma.increment) { | 
| break; | if (!(flag1 & 0x20)) { | 
| } | *off1 += (flag1 & 0x10)?1:-1; | 
| if ((dma.DMA_CMND & 2) && (dma.MACH_FLG)) { | } | 
| break; | if (!(flag2 & 0x20)) { | 
|  | *off2 += (flag2 & 0x10)?1:-1; | 
|  | } | 
 | } | } | 
 |  | dma.increment = 1; | 
 | addr = *off1; | addr = *off1; | 
 | if (flag1 & 8) { | if (flag1 & 8) { | 
 | dat = iocore_inp(addr); | dat = iocore_inp(addr); | 
 | } | } | 
 | else { | else { | 
| dat = mem_read8(addr); | dat = z80mem_read8(addr); | 
 | } | } | 
| if (dma.DMA_CMND & 1) { | if (dma.cmd & 1) { | 
 | addr = *off2; | addr = *off2; | 
 | if (flag2 & 8) { | if (flag2 & 8) { | 
 | iocore_out(addr, dat); | iocore_out(addr, dat); | 
 | } | } | 
 | else { | else { | 
| mem_write8(addr, dat); | TRACEOUT(("dma->%.4x", addr)); | 
|  | z80mem_write8(addr, dat); | 
 | } | } | 
 | } | } | 
| if (dma.DMA_CMND & 2) { | if (dma.cmd & 2) { | 
 | if (!((dat ^ dma.MACH_BYT) & (~dma.MASK_BYT))) { | if (!((dat ^ dma.MACH_BYT) & (~dma.MASK_BYT))) { | 
 |  | dma.working = FALSE; | 
 | dma.MACH_FLG = 1; | dma.MACH_FLG = 1; | 
 | } | } | 
 | } | } | 
 | if (dma.DMA_MODE != 1) { |  | 
 | dma.DMA_STOP = (dma.WR[5] ^ dma.DMA_REDY) & 8; |  | 
 | if (dma.DMA_STOP) { |  | 
 | goto dma_stop; |  | 
 | } |  | 
 | } |  | 
 | if (!(flag1 & 0x20)) { |  | 
 | *off1 += (flag1 & 0x10)?1:-1; |  | 
 | } |  | 
 | if (!(flag2 & 0x20)) { |  | 
 | *off2 += (flag2 & 0x10)?1:-1; |  | 
 | } |  | 
 |  |  | 
 | dma_stop: |  | 
 | dma.BYT_N.w++; | dma.BYT_N.w++; | 
 | if (dma.BYT_N.w == 0) { | if (dma.BYT_N.w == 0) { | 
 |  | dma.working = FALSE; | 
 | dma.ENDB_FLG = 1; | dma.ENDB_FLG = 1; | 
| break; | goto intr; | 
 | } | } | 
 | if ((dma.BYT_L.w) && (dma.BYT_L.w != 0xffff) && (dma.BYT_N.w >= (dma.BYT_L.w + 1))) { | if ((dma.BYT_L.w) && (dma.BYT_L.w != 0xffff) && (dma.BYT_N.w >= (dma.BYT_L.w + 1))) { | 
 |  | dma.working = FALSE; | 
 | dma.ENDB_FLG = 1; | dma.ENDB_FLG = 1; | 
| break; | goto intr; | 
|  | } | 
|  | if (!dma.working) { | 
|  | return; | 
 | } | } | 
| } while(dma.DMA_MODE); | } while(dma.mode); | 
|  | return; | 
 |  |  | 
 |  | intr: | 
 | if (dma.INT_ENBL) { | if (dma.INT_ENBL) { | 
| vect = 0; | ievent_set(IEVENT_DMA); | 
| if ((dma.INT_FLG & 1) && (dma.MACH_FLG)) { |  | 
| vect = 2; |  | 
| } |  | 
| else if ((dma.INT_FLG & 2) && (dma.ENDB_FLG)) { |  | 
| vect = 4; |  | 
| } |  | 
| if (vect) { |  | 
| if (dma.INT_FLG & 0x20) { |  | 
| vect += (dma.INT_VCT & 0xf9); |  | 
| } |  | 
| else { |  | 
| vect = dma.INT_VCT; |  | 
| } |  | 
| z80c_interrupt(vect); |  | 
| } |  | 
 | } | } | 
 | } | } | 
 |  |  |