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version 1.5, 2004/08/10 08:28:49
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version 1.11, 2009/03/23 15:02:25
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| #include "z80core.h" |
#include "z80core.h" |
| #include "pccore.h" |
#include "pccore.h" |
| #include "iocore.h" |
#include "iocore.h" |
| |
#include "ievent.h" |
| |
|
| |
|
| LABEL void z80dmap(void) { |
void z80dmap(void) { |
| |
|
| __asm { |
|
| mov al, dma.DMA_CMND |
|
| test al, 3 |
|
| je dmaintend |
|
| cmp dma.DMA_ENBL, 0 |
|
| je dmaintend |
|
| cmp dma.ENDB_FLG, 0 |
|
| jne dmaintend |
|
| test al, 2 |
|
| je ckcntmode |
|
| cmp dma.MACH_FLG, 0 |
|
| jne short dmaintend |
|
| ckcntmode: cmp dma.DMA_MODE, 1 |
|
| je dmaintmain |
|
| mov al, dma.WR[5] |
|
| xor al, dma.DMA_REDY |
|
| test al, 8 |
|
| je dmaintmain |
|
| dmaintend: ret |
|
| |
|
| dmaintmain: push ebx |
|
| mov ebx, offset dma.CNT_A |
|
| mov ecx, offset dma.CNT_B |
|
| |
|
| mov dx, word ptr (dma.WR[1]) |
|
| test dma.WR[0], 4 |
|
| jne dma_lp |
|
| xchg ebx, ecx |
|
| xchg dl, dh |
|
| |
|
| dma_lp: cmp dma.ENDB_FLG, 0 |
|
| jne dmalpend |
|
| test dma.DMA_CMND, 2 |
|
| je dma_lpst |
|
| cmp dma.MACH_FLG, 0 |
|
| jne dmalpend |
|
| dma_lpst: |
|
| push ecx |
|
| push edx |
|
| movzx ecx, word ptr [ebx] |
|
| test dl, 8 |
|
| jne dma_inport |
|
| call memrd8_ecx_al |
|
| dmasrcend: pop edx |
|
| pop ecx |
|
| |
|
| test dma.DMA_CMND, 1 |
|
| je dmadstend |
|
| |
|
| push eax |
|
| push ecx |
|
| push edx |
|
| movzx ecx, word ptr [ecx] |
|
| mov dl, al |
|
| test dh, 8 |
|
| jne dma_outport |
|
| call memwr8_ecx_dl |
|
| dmadstend: pop edx |
|
| pop ecx |
|
| pop eax |
|
| |
|
| test dma.DMA_CMND, 2 |
|
| je dmamachcend |
|
| xor al, dma.MACH_BYT |
|
| mov ah, dma.MASK_BYT |
|
| not ah |
|
| and al, ah |
|
| jne short dmamachcend |
|
| mov dma.MACH_FLG, 1 |
|
| dmamachcend: |
|
| cmp dma.DMA_MODE, 1 |
|
| je forcesrcaddr |
|
| mov al, dma.WR[5] |
|
| xor al, dma.DMA_REDY |
|
| and al, 8 |
|
| mov dma.DMA_STOP, al |
|
| jne dmadststpend |
|
| |
|
| forcesrcaddr: test dl, 20h |
|
| jne dmasrcstpend |
|
| test dl, 10h |
|
| je dmasrcdec |
|
| inc word ptr [ebx] |
|
| jmp dmasrcstpend |
|
| dmasrcdec: dec word ptr [ebx] |
|
| dmasrcstpend: |
|
| test dh, 20h |
|
| jne dmadststpend |
|
| test dh, 10h |
|
| je dmadstdec |
|
| inc word ptr [ecx] |
|
| jmp dmadststpend |
|
| dmadstdec: dec word ptr [ecx] |
|
| dmadststpend: |
|
| inc dma.BYT_N.w |
|
| je dmaforceend |
|
| mov ax, dma.BYT_L.w |
|
| or ax, ax |
|
| je dmplpedch // BYT_L == 0なら無制限? |
|
| inc ax |
|
| je dmplpedch // ver0.25 |
|
| cmp ax, dma.BYT_N.w |
|
| ja dmplpedch |
|
| dmaforceend: mov dma.ENDB_FLG, 1 |
|
| jmp dmalpend |
|
| |
|
| dmplpedch: cmp dma.DMA_MODE, 0 |
|
| jne dma_lp |
|
| dmalpend: |
|
| pop ebx |
|
| cmp dma.INT_ENBL, 0 |
|
| je dmaintrptend |
|
| mov dl, 2 |
|
| mov al, dma.INT_FLG |
|
| test al, 1 |
|
| je dmaintrpt2ck |
|
| cmp dma.MACH_FLG, 0 |
|
| jne dmaintrptcall |
|
| dmaintrpt2ck: mov dl, 4 |
|
| test al, 2 |
|
| je dmaintrptend |
|
| cmp dma.ENDB_FLG, 0 |
|
| je dmaintrptend |
|
| dmaintrptcall: movzx ecx, dma.INT_VCT |
|
| test al, 20h |
|
| je dma_intrpt |
|
| and cl, 0f9h |
|
| or cl, dl |
|
| dma_intrpt: jmp z80x_interrupt |
|
| dmaintrptend: ret |
|
| |
|
| |
DMACNT *cnt1; |
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DMACNT *cnt2; |
| |
UINT addr; |
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REG8 dat; |
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REG8 flag1; |
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REG8 flag2; |
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|
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#if !defined(DMAS_STOIC) |
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if (!dma.working) |
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#else |
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if (!(dma.flag & DMAF_WORKING)) |
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#endif |
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{ |
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return; |
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} |
| |
|
| dma_inport: call iocore_inp |
if (dma.WR0 & 4) { |
| jmp dmasrcend |
cnt1 = &dma.cnt_a; |
| |
cnt2 = &dma.cnt_b; |
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} |
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else { |
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cnt2 = &dma.cnt_a; |
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cnt1 = &dma.cnt_b; |
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} |
| |
|
| dma_outport: call iocore_out |
flag1 = cnt1->b.flag; |
| jmp dmadstend |
flag2 = cnt2->b.flag; |
| |
do { // dma_lp |
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CPU_REMCLOCK -= 6; |
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#if !defined(DMAS_STOIC) |
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if (dma.increment) |
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#else |
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if (dma.flag & DMAF_INCREMENT) |
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#endif |
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{ |
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if (!(flag1 & 0x20)) { |
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cnt1->w.addr += (flag1 & 0x10)?1:-1; |
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} |
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if (!(flag2 & 0x20)) { |
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cnt2->w.addr += (flag2 & 0x10)?1:-1; |
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} |
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} |
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else { |
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#if !defined(DMAS_STOIC) |
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dma.increment = 1; |
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#else |
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dma.flag |= DMAF_INCREMENT; |
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#endif |
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} |
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addr = cnt1->w.addr; |
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if (flag1 & 8) { |
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dat = iocore_inp(addr); |
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/* TRACEOUT(("dma r %.4x - %.2x", addr, dat)); */ |
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} |
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else { |
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dat = z80mem_read8(addr); |
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} |
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if (dma.WR0 & 2) { |
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if (!((dat ^ dma.MACH_BYT) & (~dma.MASK_BYT))) { |
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#if !defined(DMAS_STOIC) |
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dma.working = FALSE; |
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dma.MACH_FLG = 1; |
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#else |
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dma.flag &= ~(DMAF_WORKING | DMAF_MACH); |
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#endif |
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} |
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} |
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if (dma.WR0 & 1) { |
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addr = cnt2->w.addr; |
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if (flag2 & 8) { |
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iocore_out(addr, dat); |
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} |
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else { |
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z80mem_write8(addr, dat); |
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/* TRACEOUT(("dma w %.4x - %.2x", addr, dat)); */ |
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} |
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} |
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|
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dma.leng.w.n++; |
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if (dma.leng.w.n == 0) { |
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#if !defined(DMAS_STOIC) |
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dma.working = FALSE; |
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dma.ENDB_FLG = 1; |
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#else |
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dma.flag &= ~(DMAF_WORKING | DMAF_ENDB); |
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#endif |
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} |
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else if ((dma.leng.w.l) && ((dma.leng.w.n - 1) >= dma.leng.w.l)) { |
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#if !defined(DMAS_STOIC) |
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dma.working = FALSE; |
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dma.ENDB_FLG = 1; |
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#else |
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dma.flag &= ~(DMAF_WORKING | DMAF_ENDB); |
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#endif |
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} |
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#if !defined(DMAS_STOIC) |
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if (!dma.working) |
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#else |
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if (!(dma.flag & DMAF_WORKING)) |
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#endif |
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{ |
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goto intr; |
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} |
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} while(dma.mode); |
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return; |
| |
|
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intr: |
| |
if (dma.INT_ENBL) { |
| |
ievent_set(IEVENT_DMA); |
| } |
} |
| } |
} |
| |
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